1. Field of the Invention
The present invention relates to a system for image display, and more particularly, to an apparatus and a method of controlling image display.
2. Description of the Related Art
An abnormal frame synchronization signal, in various image-outputting devices, such as a television, is a frame synchronization signal that is inputted earlier or later than the normal timing due to an external shock or noise, channel switching, TV/VCR switching, or static electricity. An abnormal frame synchronization signal may cause a screen failure or damage the display device.
FIG. 1 is a schematic diagram of a conventional apparatus for controlling image display. Referring to FIG. 1, an input data processing unit 110 reconstructs image data that is generally input in a raster scan method into units of a bit plane with respect to a frame synchronization signal, and outputs the image data to a frame buffer control unit 130. An output data control unit 160 outputs predetermined plane data in a frame that is generated in the frame buffer control unit 130, according to a pulse width modulation (PWM) schedule, to a panel.
The frame buffer control unit 130 directly controls a first frame buffer (FB0) 140 and a second frame buffer (FB1) 150 with respect to the frame synchronization signal. That is, the frame buffer control unit 130 alternately stores data received from the input data processing unit 110 into either of the frame buffers 140 and 150 in each frame cycle, and alternately reads data from either of the frame buffers 140 and 150 according to the request of the output data control unit 160.
The PWM schedule control unit 120 performs image display routines, such as data rearrangement, in units of a frame, and controls the output data control unit 160 with respect to the frame synchronization signal to determine an output timing of each bit plane value so that the display panel can express the gradation of an image.
The conventional apparatus for controlling image display shown in FIG. 1 cannot output the data input in the same synchronization period due to the characteristic of a PWM driving method. Therefore, the apparatus show in FIG. 1 has two frame buffers, the first frame buffer 140 and the second frame buffer 150, so that the apparatus stores a frame and outputs the stored frame value when the next frame is input.
FIGS. 2A through 2G are timing diagrams of the operation of the apparatus shown in FIG. 1 when a frame synchronization signal (FIG. 2A) is normally input. Referring to FIG. 1 and FIGS. 2A through 2G, the frame buffer control unit 130 stores a frame (Frame 1 in FIG. 2B) that is input through the input data processing unit 110 in the first frame buffer (FB0 in FIG. 2E) 140, which is set as an input buffer, and if the output data control unit 160 requests frame data, reads data from the second frame buffer (FB1 in FIG. 2F) 150, which is set as an output buffer. The PWM schedule control unit 120 determines the data-read time of the output data control unit 160. Then, the frame buffer control unit 130 repeats the same operation from the beginning if another frame synchronization signal is input after the one frame cycle. Thus, the frame buffer control unit 130 resets the first frame buffer (FB0 in FIG. 2E) 140, which is an input buffer, to an output buffer and the second frame buffer (FB1 in FIG. 2F) 150, which is an output buffer, to an input buffer. The frame buffer control unit 130 stores the current frame (Frame 2 in FIG. 2B) in the second frame buffer (FB1 in FIG. 2F) 150 instead of the previous frame (Frame 0 in FIG. 2F), and outputs the frame (Frame 1 in FIG. 2G) that was stored in the first frame buffer (FB0 in FIG. 2E) 140. Accordingly, each input data signal is sequentially output to the display panel one frame cycle after the data signal was originally input.
FIGS. 3A through 3G are timing diagrams of the operation of the apparatus shown in FIG. 1 when a frame synchronization signal is abnormally input. A normal frame synchronization signal does not cause a problem in the conventional apparatus for controlling image display. However, that is not the case if channel switching, signal switching, or static electricity causes the frame synchronization signal to be input momentarily earlier or later than the normal input timing.
Referring to FIG. 1 and FIGS. 3A through 3G, if an abnormal frame synchronization signal (310 in FIG. 3A) occurs when a frame (Frame 3 in FIG. 3B) is written into the first frame buffer (FB0 in FIG. 3E) 140, the frame buffer control unit 130 begins to write new channel data (Alt Frame 0 in FIG. 3B) to the second frame buffer (FB1 in FIG. 3F) 150. At the same time, the frame buffer control unit 130 stops outputting the frame (Frame 2 in FIG. 3G) stored in the second frame buffer (FB1 in FIG. 3F) 150 in the middle of the output, and reads the data stored in the first frame buffer (FB0 in FIG. 3E) 140. Since an incomplete frame (Frame 3 in FIG. 3B) is stored in the first frame buffer (FB0 in FIG. 3E) 140, the frame buffer control unit 130 inevitably outputs the frame (Frame 3 in FIG. 3B) having damaged data. This damaged data becomes an eyesore, obstructs smooth viewing, and causes serious damage to the display panel. For example, if a ferro liquid crystal display (FLCD) suffers stress, FLCD shows a kind of irrecoverable afterimage effect. To prevent this, FLCD performs a kicking operation according to the PWM schedule that is performed at the back-end part of the one frame cycle. However, the damaged frame in the image display apparatus, which operates as shown in FIGS. 3A through 3G, cannot perform the kicking operation. Without the preventive kicking operation, the FLCD panel suffers stress and repetitive stress may have a bad effect on the display performance and the life span of the display panel.